Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\impl\gwsynthesis\psramwork.vg |
Physical Constraints File | E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psramwork.cst |
Timing Constraint File | E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psramwork.sdc |
GOWIN version | V1.9.6.02Beta |
Part Number | GW1NR-LV9LQ144PC5/I4 |
Created Time | Thu Oct 01 20:52:29 2020 |
Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C |
Hold Delay Model | Fast 1.26V 0C |
Numbers of Paths Analyzed | 6661 |
Numbers of Endpoints Analyzed | 6615 |
Numbers of Falling Endpoints | 43 |
Numbers of Setup Violated Endpoints | 2307 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk.default_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.000 | 0.000 | 3.125 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUT |
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.000 | 0.000 | 3.125 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUTP |
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 12.500 | 80.000 | 0.000 | 6.250 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUTD |
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.333 | 0.000 | 9.375 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUTD3 |
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 12.500 | 80.000 | 0.000 | 6.250 | Gowin_rPLL_inst/rpll_inst/CLKOUT | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | u_psram_top/u_psram_top/clkdiv/CLKOUT |
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk.default_clk | 50.000(MHz) | 88.318(MHz) | 6 | TOP |
2 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | 80.000(MHz) | 49.829(MHz) | 4 | TOP |
3 | DEFAULT_CLK | 100.000(MHz) | 52.063(MHz) | 6 | TOP |
No timing paths to get frequency of Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk.default_clk | Setup | 0.000 | 0 |
clk.default_clk | Hold | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | Setup | -878.742 | 923 |
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -9.208 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 18.693 |
2 | -9.010 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 18.495 |
3 | -8.702 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 18.187 |
4 | -8.556 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_5_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 18.041 |
5 | -8.530 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_12_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.571 |
6 | -8.381 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.866 |
7 | -8.286 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.327 |
8 | -8.219 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s3/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.260 |
9 | -8.206 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.247 |
10 | -8.200 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.241 |
11 | -8.154 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.639 |
12 | -8.109 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.150 |
13 | -8.005 | gw_gao_inst_0/u_la0_top/internal_register_select_2_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.490 |
14 | -7.973 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 9.014 |
15 | -7.948 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 8.989 |
16 | -7.903 | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.388 |
17 | -7.832 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.317 |
18 | -7.760 | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q | gw_gao_inst_0/u_la0_top/data_out_shift_reg_6_s1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.245 |
19 | -7.738 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 8.778 |
20 | -7.732 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D | DEFAULT_CLK:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 2.500 | 0.944 | 8.773 |
21 | -7.679 | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s1/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.592 |
22 | -7.679 | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_2_s1/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.592 |
23 | -7.679 | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_3_s1/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.592 |
24 | -7.679 | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s1/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.592 |
25 | -7.679 | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s1/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 17.592 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
2 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
3 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
4 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
5 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
6 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
7 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
8 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
9 | 0.382 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.400 |
10 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI17 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
11 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_155_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI7 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
12 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_147_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI17 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
13 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_146_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI16 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
14 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI12 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
15 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI15 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
16 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI12 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
17 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI16 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
18 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI15 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
19 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_106_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI12 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
20 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_103_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI9 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
21 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_87_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI11 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
22 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI6 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
23 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI9 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
24 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI3 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
25 | 0.586 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI8 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.678 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/u_ck_gen/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
2 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
3 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
4 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
5 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
6 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
7 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
8 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[4].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
9 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[3].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
10 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
11 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[6].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
12 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
13 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
14 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
15 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
16 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
17 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ckn_gen/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
18 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ck_gen/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
19 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
20 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[3].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
21 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
22 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
23 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
24 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mask_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
25 | -7.459 | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4/RESET | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 0.625 | 0.785 | 7.209 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.109 | gw_gao_inst_0/u_la0_top/rst_ao_s1/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[F] | DEFAULT_CLK:[R] | -1.250 | -0.529 | 1.440 |
2 | 2.110 | gw_gao_inst_0/u_la0_top/rst_ao_s1/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[F] | DEFAULT_CLK:[R] | -1.250 | -0.529 | 1.441 |
3 | 2.110 | gw_gao_inst_0/u_la0_top/rst_ao_s1/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[F] | DEFAULT_CLK:[R] | -1.250 | -0.529 | 1.441 |
4 | 3.662 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/clkdiv/RESETN | clk.default_clk:[R] | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.434 | 3.278 |
5 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_12_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
6 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/step_7_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
7 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_11_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
8 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_1_s1/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
9 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4/RESET | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
10 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_9_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
11 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/cmd_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
12 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].id_reg_13_s1/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
13 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].check_cnt_8_s1/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
14 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_17_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
15 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
16 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_3_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
17 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/rd_en_delay_all_17_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
18 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/SDTAP_0_s1/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
19 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/dll_lock_d_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
20 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_19_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
21 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/step_8_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
22 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/cats_r_21_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
23 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/q0_2_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
24 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_6_s1/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
25 | 3.934 | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_15_s0/CLEAR | clk.default_clk:[R] | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.414 | 3.573 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0 |
2 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
3 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
4 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
5 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_la0_top/data_register_136_s0 |
6 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_la0_top/data_register_104_s0 |
7 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_la0_top/data_register_88_s0 |
8 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_la0_top/data_register_80_s0 |
9 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_la0_top/data_register_76_s0 |
10 | 2.588 | 4.088 | 1.500 | Low Pulse Width | DEFAULT_CLK | gw_gao_inst_0/u_la0_top/data_register_74_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -9.208 |
Data Arrival Time | 20.326 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
15.326 | 2.172 | tNET | FF | 1 | R20C17[3][A] | gw_gao_inst_0/u_la0_top/n1691_s2/I0 |
16.564 | 1.238 | tINS | FF | 1 | R20C17[3][A] | gw_gao_inst_0/u_la0_top/n1691_s2/F |
19.087 | 2.523 | tNET | FF | 1 | R7C16[2][B] | gw_gao_inst_0/u_la0_top/n1691_s0/I1 |
20.326 | 1.238 | tINS | FF | 1 | R7C16[2][B] | gw_gao_inst_0/u_la0_top/n1691_s0/F |
20.326 | 0.000 | tNET | FF | 1 | R7C16[2][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R7C16[2][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1 | |||
11.123 | -0.480 | tSu | 1 | R7C16[2][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.785, 30.949%; route: 12.357, 66.108%; tC2Q: 0.550, 2.942% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path2
Path Summary:
Slack | -9.010 |
Data Arrival Time | 20.128 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
15.326 | 2.172 | tNET | FF | 1 | R20C17[2][B] | gw_gao_inst_0/u_la0_top/n1692_s2/I0 |
16.564 | 1.238 | tINS | FF | 1 | R20C17[2][B] | gw_gao_inst_0/u_la0_top/n1692_s2/F |
18.890 | 2.326 | tNET | FF | 1 | R7C17[0][A] | gw_gao_inst_0/u_la0_top/n1692_s0/I1 |
20.128 | 1.238 | tINS | FF | 1 | R7C17[0][A] | gw_gao_inst_0/u_la0_top/n1692_s0/F |
20.128 | 0.000 | tNET | FF | 1 | R7C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R7C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1 | |||
11.123 | -0.480 | tSu | 1 | R7C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.785, 31.280%; route: 12.160, 65.747%; tC2Q: 0.550, 2.974% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path3
Path Summary:
Slack | -8.702 |
Data Arrival Time | 19.820 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
15.315 | 2.161 | tNET | FF | 1 | R20C19[1][B] | gw_gao_inst_0/u_la0_top/n1694_s2/I0 |
16.553 | 1.238 | tINS | FF | 1 | R20C19[1][B] | gw_gao_inst_0/u_la0_top/n1694_s2/F |
18.502 | 1.948 | tNET | FF | 1 | R8C19[1][A] | gw_gao_inst_0/u_la0_top/n1694_s0/I1 |
19.820 | 1.319 | tINS | FF | 1 | R8C19[1][A] | gw_gao_inst_0/u_la0_top/n1694_s0/F |
19.820 | 0.000 | tNET | FF | 1 | R8C19[1][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R8C19[1][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1 | |||
11.123 | -0.480 | tSu | 1 | R8C19[1][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.866, 32.251%; route: 11.772, 64.725%; tC2Q: 0.550, 3.024% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path4
Path Summary:
Slack | -8.556 |
Data Arrival Time | 19.675 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_5_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
14.747 | 1.593 | tNET | FF | 1 | R18C19[0][A] | gw_gao_inst_0/u_la0_top/n1698_s2/I0 |
15.733 | 0.986 | tINS | FF | 1 | R18C19[0][A] | gw_gao_inst_0/u_la0_top/n1698_s2/F |
18.436 | 2.703 | tNET | FF | 1 | R7C16[0][A] | gw_gao_inst_0/u_la0_top/n1698_s0/I1 |
19.675 | 1.238 | tINS | FF | 1 | R7C16[0][A] | gw_gao_inst_0/u_la0_top/n1698_s0/F |
19.675 | 0.000 | tNET | FF | 1 | R7C16[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R7C16[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_5_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_5_s1 | |||
11.123 | -0.480 | tSu | 1 | R7C16[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.533, 30.669%; route: 11.958, 66.282%; tC2Q: 0.550, 3.049% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path5
Path Summary:
Slack | -8.530 |
Data Arrival Time | 21.204 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_12_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_12_s0/CLK |
12.183 | 0.550 | tC2Q | RF | 2 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_12_s0/Q |
14.130 | 1.947 | tNET | FF | 1 | R20C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I0 |
15.368 | 1.238 | tINS | FF | 1 | R20C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F |
16.353 | 0.985 | tNET | FF | 1 | R18C17[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2 |
17.672 | 1.319 | tINS | FF | 2 | R18C17[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
18.643 | 0.971 | tNET | FF | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I0 |
19.629 | 0.986 | tINS | FF | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F |
20.217 | 0.588 | tNET | FF | 1 | R18C16[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n743_s4/I2 |
21.204 | 0.986 | tINS | FF | 1 | R18C16[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n743_s4/F |
21.204 | 0.000 | tNET | FF | 1 | R18C16[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R18C16[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8 | |||
12.679 | -0.480 | tSu | 1 | R18C16[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.530, 47.332%; route: 4.491, 46.921%; tC2Q: 0.550, 5.747% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path6
Path Summary:
Slack | -8.381 |
Data Arrival Time | 19.499 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
15.326 | 2.172 | tNET | FF | 1 | R20C17[2][A] | gw_gao_inst_0/u_la0_top/n1688_s2/I0 |
16.564 | 1.238 | tINS | FF | 1 | R20C17[2][A] | gw_gao_inst_0/u_la0_top/n1688_s2/F |
18.513 | 1.948 | tNET | FF | 1 | R8C17[0][A] | gw_gao_inst_0/u_la0_top/n1688_s0/I1 |
19.499 | 0.986 | tINS | FF | 1 | R8C17[0][A] | gw_gao_inst_0/u_la0_top/n1688_s0/F |
19.499 | 0.000 | tNET | FF | 1 | R8C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R8C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1 | |||
11.123 | -0.480 | tSu | 1 | R8C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.533, 30.971%; route: 11.783, 65.951%; tC2Q: 0.550, 3.078% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path7
Path Summary:
Slack | -8.286 |
Data Arrival Time | 20.960 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.641 | 1.578 | tNET | FF | 1 | R18C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n763_s0/I3 |
20.960 | 1.319 | tINS | FF | 1 | R18C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n763_s0/F |
20.960 | 0.000 | tNET | FF | 1 | R18C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R18C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 | |||
12.679 | -0.480 | tSu | 1 | R18C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.708, 50.473%; route: 4.069, 43.630%; tC2Q: 0.550, 5.897% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path8
Path Summary:
Slack | -8.219 |
Data Arrival Time | 20.893 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s3 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.655 | 1.592 | tNET | FF | 1 | R23C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n768_s2/I3 |
20.893 | 1.238 | tINS | FF | 1 | R23C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n768_s2/F |
20.893 | 0.000 | tNET | FF | 1 | R23C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R23C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s3/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s3 | |||
12.679 | -0.480 | tSu | 1 | R23C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s3 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.627, 49.969%; route: 4.083, 44.092%; tC2Q: 0.550, 5.939% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path9
Path Summary:
Slack | -8.206 |
Data Arrival Time | 20.880 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.641 | 1.578 | tNET | FF | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n766_s0/I3 |
20.880 | 1.238 | tINS | FF | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n766_s0/F |
20.880 | 0.000 | tNET | FF | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 | |||
12.679 | -0.480 | tSu | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.627, 50.042%; route: 4.069, 44.009%; tC2Q: 0.550, 5.948% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path10
Path Summary:
Slack | -8.200 |
Data Arrival Time | 20.874 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.636 | 1.573 | tNET | FF | 1 | R23C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n760_s0/I3 |
20.874 | 1.238 | tINS | FF | 1 | R23C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n760_s0/F |
20.874 | 0.000 | tNET | FF | 1 | R23C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R23C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 | |||
12.679 | -0.480 | tSu | 1 | R23C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.627, 50.072%; route: 4.064, 43.976%; tC2Q: 0.550, 5.952% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path11
Path Summary:
Slack | -8.154 |
Data Arrival Time | 19.272 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
14.560 | 1.406 | tNET | FF | 1 | R18C18[3][A] | gw_gao_inst_0/u_la0_top/n1696_s2/I0 |
15.798 | 1.238 | tINS | FF | 1 | R18C18[3][A] | gw_gao_inst_0/u_la0_top/n1696_s2/F |
18.521 | 2.723 | tNET | FF | 1 | R9C17[0][A] | gw_gao_inst_0/u_la0_top/n1696_s0/I1 |
19.272 | 0.751 | tINS | FF | 1 | R9C17[0][A] | gw_gao_inst_0/u_la0_top/n1696_s0/F |
19.272 | 0.000 | tNET | FF | 1 | R9C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R9C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1 | |||
11.123 | -0.480 | tSu | 1 | R9C17[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.298, 30.036%; route: 11.791, 66.846%; tC2Q: 0.550, 3.118% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path12
Path Summary:
Slack | -8.109 |
Data Arrival Time | 20.783 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
12.183 | 0.550 | tC2Q | RF | 2 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
14.314 | 2.131 | tNET | FF | 1 | R20C18[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n843_s13/I2 |
15.633 | 1.319 | tINS | FF | 1 | R20C18[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n843_s13/F |
15.640 | 0.007 | tNET | FF | 1 | R20C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n843_s8/I3 |
16.626 | 0.986 | tINS | FF | 1 | R20C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n843_s8/F |
16.633 | 0.007 | tNET | FF | 1 | R20C18[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n843_s4/I2 |
17.952 | 1.319 | tINS | FF | 11 | R20C18[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n843_s4/F |
19.545 | 1.593 | tNET | FF | 1 | R21C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n848_s1/I2 |
20.783 | 1.238 | tINS | FF | 1 | R21C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n848_s1/F |
20.783 | 0.000 | tNET | FF | 1 | R21C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R21C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 | |||
12.679 | -0.480 | tSu | 1 | R21C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.862, 53.140%; route: 3.738, 40.849%; tC2Q: 0.550, 6.011% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path13
Path Summary:
Slack | -8.005 |
Data Arrival Time | 19.123 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_2_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R22C17[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_2_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 5 | R22C17[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_2_s0/Q |
4.334 | 2.150 | tNET | FF | 1 | R21C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s10/I0 |
5.652 | 1.319 | tINS | FF | 3 | R21C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s10/F |
9.549 | 3.897 | tNET | FF | 1 | R8C17[3][A] | gw_gao_inst_0/u_la0_top/n1702_s4/I2 |
10.300 | 0.751 | tINS | FF | 9 | R8C17[3][A] | gw_gao_inst_0/u_la0_top/n1702_s4/F |
13.043 | 2.743 | tNET | FF | 1 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/n1702_s7/I3 |
14.362 | 1.319 | tINS | FF | 1 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/n1702_s7/F |
16.892 | 2.530 | tNET | FF | 1 | R8C19[3][B] | gw_gao_inst_0/u_la0_top/n1702_s2/I1 |
17.878 | 0.986 | tINS | FF | 1 | R8C19[3][B] | gw_gao_inst_0/u_la0_top/n1702_s2/F |
17.885 | 0.007 | tNET | FF | 1 | R8C19[1][B] | gw_gao_inst_0/u_la0_top/n1702_s0/I1 |
19.123 | 1.238 | tINS | FF | 1 | R8C19[1][B] | gw_gao_inst_0/u_la0_top/n1702_s0/F |
19.123 | 0.000 | tNET | FF | 1 | R8C19[1][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R8C19[1][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1 | |||
11.123 | -0.480 | tSu | 1 | R8C19[1][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.614, 32.096%; route: 11.327, 64.760%; tC2Q: 0.550, 3.145% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path14
Path Summary:
Slack | -7.973 |
Data Arrival Time | 20.647 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.660 | 1.598 | tNET | FF | 1 | R18C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n767_s0/I3 |
20.647 | 0.986 | tINS | FF | 1 | R18C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n767_s0/F |
20.647 | 0.000 | tNET | FF | 1 | R18C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R18C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 | |||
12.679 | -0.480 | tSu | 1 | R18C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.375, 48.540%; route: 4.088, 45.358%; tC2Q: 0.550, 6.102% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path15
Path Summary:
Slack | -7.948 |
Data Arrival Time | 20.622 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.636 | 1.573 | tNET | FF | 1 | R23C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s0/I3 |
20.622 | 0.986 | tINS | FF | 1 | R23C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s0/F |
20.622 | 0.000 | tNET | FF | 1 | R23C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R23C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 | |||
12.679 | -0.480 | tSu | 1 | R23C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.375, 48.672%; route: 4.064, 45.209%; tC2Q: 0.550, 6.119% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path16
Path Summary:
Slack | -7.903 |
Data Arrival Time | 19.021 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 2 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q |
4.314 | 2.131 | tNET | FF | 1 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/I3 |
5.633 | 1.319 | tINS | FF | 8 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/F |
6.823 | 1.189 | tNET | FF | 1 | R14C20[0][B] | gw_gao_inst_0/u_la0_top/n1536_s5/I0 |
8.141 | 1.319 | tINS | FF | 2 | R14C20[0][B] | gw_gao_inst_0/u_la0_top/n1536_s5/F |
8.155 | 0.013 | tNET | FF | 1 | R14C20[1][B] | gw_gao_inst_0/u_la0_top/n1536_s2/I3 |
9.473 | 1.319 | tINS | FF | 169 | R14C20[1][B] | gw_gao_inst_0/u_la0_top/n1536_s2/F |
12.209 | 2.735 | tNET | FF | 1 | R15C18[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s3/I3 |
13.447 | 1.238 | tINS | FF | 170 | R15C18[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s3/F |
17.782 | 4.335 | tNET | FF | 1 | R4C17[1][A] | gw_gao_inst_0/u_la0_top/n1704_s1/I0 |
19.021 | 1.238 | tINS | FF | 1 | R4C17[1][A] | gw_gao_inst_0/u_la0_top/n1704_s1/F |
19.021 | 0.000 | tNET | FF | 1 | R4C17[1][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R4C17[1][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s1 | |||
11.123 | -0.480 | tSu | 1 | R4C17[1][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_168_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 6.433, 36.999%; route: 10.404, 59.838%; tC2Q: 0.550, 3.163% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path17
Path Summary:
Slack | -7.832 |
Data Arrival Time | 18.950 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
14.554 | 1.401 | tNET | FF | 1 | R17C19[3][B] | gw_gao_inst_0/u_la0_top/n1699_s2/I0 |
15.305 | 0.751 | tINS | FF | 1 | R17C19[3][B] | gw_gao_inst_0/u_la0_top/n1699_s2/F |
17.631 | 2.326 | tNET | FF | 1 | R8C18[0][A] | gw_gao_inst_0/u_la0_top/n1699_s0/I1 |
18.950 | 1.319 | tINS | FF | 1 | R8C18[0][A] | gw_gao_inst_0/u_la0_top/n1699_s0/F |
18.950 | 0.000 | tNET | FF | 1 | R8C18[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R8C18[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1 | |||
11.123 | -0.480 | tSu | 1 | R8C18[0][A] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.378, 31.059%; route: 11.388, 65.765%; tC2Q: 0.550, 3.176% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path18
Path Summary:
Slack | -7.760 |
Data Arrival Time | 18.878 |
Data Required Time | 11.118 |
From | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0 |
To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_6_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 11 | R21C20[2][A] | gw_gao_inst_0/u_la0_top/internal_register_select_4_s0/Q |
5.117 | 2.933 | tNET | FF | 1 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/I0 |
5.868 | 0.751 | tINS | FF | 4 | R8C17[1][A] | gw_gao_inst_0/u_la0_top/n1700_s11/F |
8.409 | 2.542 | tNET | FF | 1 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/I3 |
9.648 | 1.238 | tINS | FF | 8 | R21C19[3][A] | gw_gao_inst_0/u_la0_top/n1700_s17/F |
11.835 | 2.187 | tNET | FF | 1 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/I1 |
13.154 | 1.319 | tINS | FF | 12 | R9C18[1][B] | gw_gao_inst_0/u_la0_top/n1688_s7/F |
14.747 | 1.593 | tNET | FF | 1 | R18C19[3][B] | gw_gao_inst_0/u_la0_top/n1697_s2/I0 |
15.985 | 1.238 | tINS | FF | 1 | R18C19[3][B] | gw_gao_inst_0/u_la0_top/n1697_s2/F |
18.126 | 2.141 | tNET | FF | 1 | R7C19[0][B] | gw_gao_inst_0/u_la0_top/n1697_s0/I1 |
18.878 | 0.751 | tINS | FF | 1 | R7C19[0][B] | gw_gao_inst_0/u_la0_top/n1697_s0/F |
18.878 | 0.000 | tNET | FF | 1 | R7C19[0][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R7C19[0][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_6_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/data_out_shift_reg_6_s1 | |||
11.123 | -0.480 | tSu | 1 | R7C19[0][B] | gw_gao_inst_0/u_la0_top/data_out_shift_reg_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.298, 30.723%; route: 11.397, 66.088%; tC2Q: 0.550, 3.189% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path19
Path Summary:
Slack | -7.738 |
Data Arrival Time | 20.411 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.660 | 1.598 | tNET | FF | 1 | R18C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n764_s0/I3 |
20.411 | 0.751 | tINS | FF | 1 | R18C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n764_s0/F |
20.411 | 0.000 | tNET | FF | 1 | R18C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R18C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 | |||
12.679 | -0.480 | tSu | 1 | R18C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.140, 47.161%; route: 4.088, 46.573%; tC2Q: 0.550, 6.265% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path20
Path Summary:
Slack | -7.732 |
Data Arrival Time | 20.406 |
Data Required Time | 12.674 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK |
12.183 | 0.550 | tC2Q | RR | 2 | R21C17[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q |
12.690 | 0.507 | tNET | RR | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/I3 |
14.009 | 1.319 | tINS | RF | 1 | R21C16[0][B] | gw_gao_inst_0/u_la0_top/triger_s5/F |
14.974 | 0.965 | tNET | FF | 1 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/I3 |
15.725 | 0.751 | tINS | FF | 8 | R21C16[0][A] | gw_gao_inst_0/u_la0_top/triger_s2/F |
16.744 | 1.019 | tNET | FF | 1 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/I2 |
18.063 | 1.319 | tINS | FF | 11 | R20C16[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n759_s4/F |
19.655 | 1.592 | tNET | FF | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n762_s0/I3 |
20.406 | 0.751 | tINS | FF | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n762_s0/F |
20.406 | 0.000 | tNET | FF | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
12.896 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
13.189 | 0.293 | tNET | RR | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
13.159 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 | |||
12.679 | -0.480 | tSu | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.944 |
Setup Relationship | 2.500 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 4.140, 47.191%; route: 4.083, 46.540%; tC2Q: 0.550, 6.269% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.293, 100.000% |
Path21
Path Summary:
Slack | -7.679 |
Data Arrival Time | 19.225 |
Data Required Time | 11.546 |
From | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 2 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q |
4.314 | 2.131 | tNET | FF | 1 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/I3 |
5.633 | 1.319 | tINS | FF | 8 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/F |
7.430 | 1.797 | tNET | FF | 1 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/I3 |
8.668 | 1.238 | tINS | FF | 2 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/F |
11.006 | 2.338 | tNET | FF | 1 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/I2 |
12.245 | 1.238 | tINS | FF | 35 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/F |
13.250 | 1.005 | tNET | FF | 1 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/I1 |
14.488 | 1.238 | tINS | FF | 12 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/F |
16.463 | 1.975 | tNET | FF | 1 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I2 |
17.213 | 0.750 | tINS | FR | 32 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F |
19.225 | 2.013 | tNET | RR | 1 | R24C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R24C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s1 | |||
11.551 | -0.052 | tSu | 1 | R24C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.784, 32.878%; route: 11.258, 63.996%; tC2Q: 0.550, 3.126% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path22
Path Summary:
Slack | -7.679 |
Data Arrival Time | 19.225 |
Data Required Time | 11.546 |
From | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_2_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 2 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q |
4.314 | 2.131 | tNET | FF | 1 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/I3 |
5.633 | 1.319 | tINS | FF | 8 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/F |
7.430 | 1.797 | tNET | FF | 1 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/I3 |
8.668 | 1.238 | tINS | FF | 2 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/F |
11.006 | 2.338 | tNET | FF | 1 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/I2 |
12.245 | 1.238 | tINS | FF | 35 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/F |
13.250 | 1.005 | tNET | FF | 1 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/I1 |
14.488 | 1.238 | tINS | FF | 12 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/F |
16.463 | 1.975 | tNET | FF | 1 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I2 |
17.213 | 0.750 | tINS | FR | 32 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F |
19.225 | 2.013 | tNET | RR | 1 | R24C17[0][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R24C17[0][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_2_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_2_s1 | |||
11.551 | -0.052 | tSu | 1 | R24C17[0][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.784, 32.878%; route: 11.258, 63.996%; tC2Q: 0.550, 3.126% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path23
Path Summary:
Slack | -7.679 |
Data Arrival Time | 19.225 |
Data Required Time | 11.546 |
From | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_3_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 2 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q |
4.314 | 2.131 | tNET | FF | 1 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/I3 |
5.633 | 1.319 | tINS | FF | 8 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/F |
7.430 | 1.797 | tNET | FF | 1 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/I3 |
8.668 | 1.238 | tINS | FF | 2 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/F |
11.006 | 2.338 | tNET | FF | 1 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/I2 |
12.245 | 1.238 | tINS | FF | 35 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/F |
13.250 | 1.005 | tNET | FF | 1 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/I1 |
14.488 | 1.238 | tINS | FF | 12 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/F |
16.463 | 1.975 | tNET | FF | 1 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I2 |
17.213 | 0.750 | tINS | FR | 32 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F |
19.225 | 2.013 | tNET | RR | 1 | R24C17[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R24C17[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_3_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_3_s1 | |||
11.551 | -0.052 | tSu | 1 | R24C17[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.784, 32.878%; route: 11.258, 63.996%; tC2Q: 0.550, 3.126% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path24
Path Summary:
Slack | -7.679 |
Data Arrival Time | 19.225 |
Data Required Time | 11.546 |
From | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 2 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q |
4.314 | 2.131 | tNET | FF | 1 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/I3 |
5.633 | 1.319 | tINS | FF | 8 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/F |
7.430 | 1.797 | tNET | FF | 1 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/I3 |
8.668 | 1.238 | tINS | FF | 2 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/F |
11.006 | 2.338 | tNET | FF | 1 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/I2 |
12.245 | 1.238 | tINS | FF | 35 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/F |
13.250 | 1.005 | tNET | FF | 1 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/I1 |
14.488 | 1.238 | tINS | FF | 12 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/F |
16.463 | 1.975 | tNET | FF | 1 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I2 |
17.213 | 0.750 | tINS | FR | 32 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F |
19.225 | 2.013 | tNET | RR | 1 | R24C17[1][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R24C17[1][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s1 | |||
11.551 | -0.052 | tSu | 1 | R24C17[1][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.784, 32.878%; route: 11.258, 63.996%; tC2Q: 0.550, 3.126% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Path25
Path Summary:
Slack | -7.679 |
Data Arrival Time | 19.225 |
Data Required Time | 11.546 |
From | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
0.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
1.633 | 1.633 | tNET | RR | 1 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
2.183 | 0.550 | tC2Q | RF | 2 | R12C22[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q |
4.314 | 2.131 | tNET | FF | 1 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/I3 |
5.633 | 1.319 | tINS | FF | 8 | R12C22[0][B] | gw_gao_inst_0/u_la0_top/n20_s1/F |
7.430 | 1.797 | tNET | FF | 1 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/I3 |
8.668 | 1.238 | tINS | FF | 2 | R17C20[1][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s24/F |
11.006 | 2.338 | tNET | FF | 1 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/I2 |
12.245 | 1.238 | tINS | FF | 35 | R23C19[0][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s18/F |
13.250 | 1.005 | tNET | FF | 1 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/I1 |
14.488 | 1.238 | tINS | FF | 12 | R22C17[1][B] | gw_gao_inst_0/u_la0_top/op_reg_en_s17/F |
16.463 | 1.975 | tNET | FF | 1 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I2 |
17.213 | 0.750 | tINS | FR | 32 | R16C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F |
19.225 | 2.013 | tNET | RR | 1 | R24C17[2][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
11.633 | 1.633 | tNET | RR | 1 | R24C17[2][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s1/CLK |
11.603 | -0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s1 | |||
11.551 | -0.052 | tSu | 1 | R24C17[2][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Arrival Data Path Delay | cell: 5.784, 32.878%; route: 11.258, 63.996%; tC2Q: 0.550, 3.126% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.633, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path2
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[4] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[4] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[4] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path3
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R28[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R28[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R28[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path4
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path5
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path6
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path7
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path8
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R28[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R28[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R28[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path9
Path Summary:
Slack | 0.382 |
Data Arrival Time | 1.018 |
Data Required Time | 0.636 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.018 | 0.400 | tC2Q | RR | 17 | R20C16[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.018 | 0.000 | tNET | RR | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s | |||
0.666 | 0.018 | tHld | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.400, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path10
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C9[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C9[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI17 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path11
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_155_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C8[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_155_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C8[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_155_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI7 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path12
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_147_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C21[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_147_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C21[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_147_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI17 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path13
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_146_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R11C21[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_146_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R11C21[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_146_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI16 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path14
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C21[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI12 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path15
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C12[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C12[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI15 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path16
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C12[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C12[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI12 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path17
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C6[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C6[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI16 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path18
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C6[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C6[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI15 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path19
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_106_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R11C6[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_106_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R11C6[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_106_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI12 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path20
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_103_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C5[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_103_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C5[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_103_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI9 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path21
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_87_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R11C24[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_87_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R11C24[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_87_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI11 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path22
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C23[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C23[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path23
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C8[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C8[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI9 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[1] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path24
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C23[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C23[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path25
Path Summary:
Slack | 0.586 |
Data Arrival Time | 1.295 |
Data Required Time | 0.710 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C20[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/CLK |
1.018 | 0.400 | tC2Q | RF | 1 | R9C20[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/Q |
1.295 | 0.278 | tNET | FF | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI8 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.648 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s | |||
0.740 | 0.092 | tHld | 1 | BSRAM_R10[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/u_ck_gen |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL23[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/u_ck_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL23[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/u_ck_gen/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/u_ck_gen | |||
40.991 | -0.054 | tSu | 1 | IOL23[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/u_ck_gen |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path2
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL27[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL27[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL27[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path3
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL26[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL26[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL26[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path4
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL26[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL26[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL26[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path5
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL21[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL21[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL21[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path6
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL25[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL25[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL25[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path7
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[5].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL26[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL26[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[5].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[5].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL26[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[5].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path8
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[4].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL25[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[4].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL25[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[4].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[4].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL25[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[4].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path9
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[3].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL21[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[3].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL21[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[3].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[3].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL21[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[3].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path10
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL20[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL20[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL20[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path11
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[6].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL26[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[6].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL26[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[6].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[6].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL26[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[6].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path12
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL17[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL17[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL17[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path13
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL16[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL16[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL16[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path14
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL15[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL15[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL15[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path15
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL9[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL9[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL9[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path16
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL6[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL6[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL6[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path17
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ckn_gen |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL7[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ckn_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL7[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ckn_gen/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ckn_gen | |||
40.991 | -0.054 | tSu | 1 | IOL7[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ckn_gen |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path18
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ck_gen |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL8[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ck_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL8[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ck_gen/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ck_gen | |||
40.991 | -0.054 | tSu | 1 | IOL8[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_ck_gen |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path19
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 4 | IOL20[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL20[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 | |||
40.991 | -0.054 | tSu | 1 | IOL20[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path20
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[3].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL6[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[3].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL6[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[3].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[3].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL6[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[3].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path21
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL4[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL4[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL4[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path22
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL3[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL3[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL3[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path23
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL2[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL2[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL2[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path24
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mask_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL17[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mask_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL17[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mask_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mask_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL17[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mask_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Path25
Path Summary:
Slack | -7.459 |
Data Arrival Time | 48.445 |
Data Required Time | 40.986 |
From | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | clk.default_clk | ||||
40.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
40.943 | 0.943 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
41.235 | 0.293 | tNET | RR | 1 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/CLK |
41.785 | 0.550 | tC2Q | RF | 8 | R6C14[0][A] | u_psram_top/u_psram_top/u_psram_sync/cs_memsync_3_s0/Q |
43.960 | 2.174 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I0 |
44.711 | 0.751 | tINS | FF | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
48.445 | 3.734 | tNET | FF | 2 | IOL6[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.625 | 40.625 | active clock edge time | ||||
40.625 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
40.625 | 0.000 | tCL | FF | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
40.625 | 0.000 | tNET | FF | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
40.929 | 0.304 | tINS | FF | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
41.075 | 0.146 | tNET | FF | 1 | IOL6[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4/FCLK |
41.045 | -0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4 | |||
40.991 | -0.054 | tSu | 1 | IOL6[B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4 |
Path Statistics:
Clock Skew | -0.785 |
Setup Relationship | 0.625 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.943, 76.304%; route: 0.293, 23.696% |
Arrival Data Path Delay | cell: 0.751, 10.420%; route: 5.908, 81.951%; tC2Q: 0.550, 7.629% |
Required Clock Path Delay | cell: 0.304, 67.615%; route: 0.146, 32.385% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.109 |
Data Arrival Time | 33.321 |
Data Required Time | 31.212 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s1 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
31.250 | 31.250 | active clock edge time | ||||
31.250 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
31.646 | 0.396 | tCL | FF | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
31.881 | 0.234 | tNET | FF | 1 | R18C16[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK |
32.281 | 0.400 | tC2Q | FR | 44 | R18C16[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s1/Q |
33.321 | 1.040 | tNET | RR | 1 | R17C21[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
30.000 | 30.000 | active clock edge time | ||||
30.000 | 0.000 | DEFAULT_CLK | ||||
30.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
30.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
31.159 | 1.159 | tNET | RR | 1 | R17C21[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK |
31.189 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 | |||
31.207 | 0.018 | tHld | 1 | R17C21[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Path Statistics:
Clock Skew | 0.529 |
Hold Relationship | -1.250 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.234, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.040, 72.228%; tC2Q: 0.400, 27.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.159, 100.000% |
Path2
Path Summary:
Slack | 2.110 |
Data Arrival Time | 33.322 |
Data Required Time | 31.212 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s1 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
31.250 | 31.250 | active clock edge time | ||||
31.250 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
31.646 | 0.396 | tCL | FF | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
31.881 | 0.234 | tNET | FF | 1 | R18C16[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK |
32.281 | 0.400 | tC2Q | FR | 44 | R18C16[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s1/Q |
33.322 | 1.041 | tNET | RR | 1 | R22C19[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
30.000 | 30.000 | active clock edge time | ||||
30.000 | 0.000 | DEFAULT_CLK | ||||
30.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
30.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
31.159 | 1.159 | tNET | RR | 1 | R22C19[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
31.189 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 | |||
31.207 | 0.018 | tHld | 1 | R22C19[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Path Statistics:
Clock Skew | 0.529 |
Hold Relationship | -1.250 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.234, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.041, 72.250%; tC2Q: 0.400, 27.750% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.159, 100.000% |
Path3
Path Summary:
Slack | 2.110 |
Data Arrival Time | 33.322 |
Data Required Time | 31.212 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s1 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
31.250 | 31.250 | active clock edge time | ||||
31.250 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
31.646 | 0.396 | tCL | FF | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
31.881 | 0.234 | tNET | FF | 1 | R18C16[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK |
32.281 | 0.400 | tC2Q | FR | 44 | R18C16[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s1/Q |
33.322 | 1.041 | tNET | RR | 1 | R22C19[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
30.000 | 30.000 | active clock edge time | ||||
30.000 | 0.000 | DEFAULT_CLK | ||||
30.000 | 0.000 | tCL | RR | 1 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
30.000 | 0.000 | tINS | RR | 642 | UNPLACED | gw_gao_inst_0/u_gw_jtag/tck_o |
31.159 | 1.159 | tNET | RR | 1 | R22C19[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
31.189 | 0.030 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 | |||
31.207 | 0.018 | tHld | 1 | R22C19[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
Path Statistics:
Clock Skew | 0.529 |
Hold Relationship | -1.250 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.234, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.041, 72.250%; tC2Q: 0.400, 27.750% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.159, 100.000% |
Path4
Path Summary:
Slack | 3.662 |
Data Arrival Time | 4.310 |
Data Required Time | 0.648 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/clkdiv |
Launch Clk | clk.default_clk:[R] |
Latch Clk | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][A] | u_psram_top/u_psram_top/n502_s1/I1 |
2.444 | 0.722 | tINS | FF | 1 | R5C2[0][A] | u_psram_top/u_psram_top/n502_s1/F |
4.310 | 1.865 | tNET | FF | 1 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/RESETN |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R | Gowin_rPLL_inst/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN |
0.255 | 0.255 | tINS | RR | 41 | UNPLACED | u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT |
0.598 | 0.343 | tNET | RR | 5 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/HCLKIN |
0.628 | 0.030 | tUnc | u_psram_top/u_psram_top/clkdiv | |||
0.643 | 0.015 | tHld | 1 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv |
Path Statistics:
Clock Skew | -0.434 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.722, 22.039%; route: 2.155, 65.757%; tC2Q: 0.400, 12.203% |
Required Clock Path Delay | cell: 0.255, 42.689%; route: 0.343, 57.311% |
Path5
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_12_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R18C11[1][B] | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_12_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R18C11[1][B] | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_12_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_12_s0 | |||
0.666 | 0.018 | tHld | 1 | R18C11[1][B] | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_12_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path6
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/step_7_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R13C6[1][A] | u_psram_top/u_psram_top/u_psram_wd/step_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R13C6[1][A] | u_psram_top/u_psram_top/u_psram_wd/step_7_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/step_7_s0 | |||
0.666 | 0.018 | tHld | 1 | R13C6[1][A] | u_psram_top/u_psram_top/u_psram_wd/step_7_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path7
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_11_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R7C8[2][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R7C8[2][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_11_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_11_s0 | |||
0.666 | 0.018 | tHld | 1 | R7C8[2][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_11_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path8
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_1_s1 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R15C10[0][A] | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R15C10[0][A] | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_1_s1/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_1_s1 | |||
0.666 | 0.018 | tHld | 1 | R15C10[0][A] | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_1_s1 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path9
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 2 | IOL4[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | IOL4[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4/PCLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 | |||
0.666 | 0.018 | tHld | 1 | IOL4[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path10
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_9_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R18C11[0][A] | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R18C11[0][A] | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_9_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_9_s0 | |||
0.666 | 0.018 | tHld | 1 | R18C11[0][A] | u_psram_top/u_psram_top/u_psram_init/tvcs_cnt_9_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path11
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/cmd_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R16C9[0][A] | u_psram_top/u_psram_top/u_psram_init/cmd_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R16C9[0][A] | u_psram_top/u_psram_top/u_psram_init/cmd_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/cmd_s0 | |||
0.666 | 0.018 | tHld | 1 | R16C9[0][A] | u_psram_top/u_psram_top/u_psram_init/cmd_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path12
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].id_reg_13_s1 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R14C3[2][A] | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].id_reg_13_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R14C3[2][A] | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].id_reg_13_s1/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].id_reg_13_s1 | |||
0.666 | 0.018 | tHld | 1 | R14C3[2][A] | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].id_reg_13_s1 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path13
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].check_cnt_8_s1 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R21C5[0][B] | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].check_cnt_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R21C5[0][B] | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].check_cnt_8_s1/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].check_cnt_8_s1 | |||
0.666 | 0.018 | tHld | 1 | R21C5[0][B] | u_psram_top/u_psram_top/u_psram_init/read_calibration[1].check_cnt_8_s1 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path14
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_17_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R4C8[1][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_17_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R4C8[1][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_17_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_17_s0 | |||
0.666 | 0.018 | tHld | 1 | R4C8[1][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_17_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path15
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 2 | IOL15[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | IOL15[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/PCLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4 | |||
0.666 | 0.018 | tHld | 1 | IOL15[A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path16
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_3_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R8C8[1][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R8C8[1][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_3_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_3_s0 | |||
0.666 | 0.018 | tHld | 1 | R8C8[1][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_3_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path17
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/rd_en_delay_all_17_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R8C11[1][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/rd_en_delay_all_17_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R8C11[1][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/rd_en_delay_all_17_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/rd_en_delay_all_17_s0 | |||
0.666 | 0.018 | tHld | 1 | R8C11[1][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/rd_en_delay_all_17_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path18
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/SDTAP_0_s1 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R18C7[0][A] | u_psram_top/u_psram_top/u_psram_init/SDTAP_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R18C7[0][A] | u_psram_top/u_psram_top/u_psram_init/SDTAP_0_s1/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/SDTAP_0_s1 | |||
0.666 | 0.018 | tHld | 1 | R18C7[0][A] | u_psram_top/u_psram_top/u_psram_init/SDTAP_0_s1 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path19
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/dll_lock_d_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R13C4[0][B] | u_psram_top/u_psram_top/u_psram_wd/dll_lock_d_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R13C4[0][B] | u_psram_top/u_psram_top/u_psram_wd/dll_lock_d_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/dll_lock_d_s0 | |||
0.666 | 0.018 | tHld | 1 | R13C4[0][B] | u_psram_top/u_psram_top/u_psram_wd/dll_lock_d_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path20
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_19_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R7C5[0][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_19_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R7C5[0][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_19_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_19_s0 | |||
0.666 | 0.018 | tHld | 1 | R7C5[0][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_19_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path21
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/step_8_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R13C6[1][B] | u_psram_top/u_psram_top/u_psram_wd/step_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R13C6[1][B] | u_psram_top/u_psram_top/u_psram_wd/step_8_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/step_8_s0 | |||
0.666 | 0.018 | tHld | 1 | R13C6[1][B] | u_psram_top/u_psram_top/u_psram_wd/step_8_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path22
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/cats_r_21_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R9C10[0][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/cats_r_21_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R9C10[0][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/cats_r_21_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/cats_r_21_s0 | |||
0.666 | 0.018 | tHld | 1 | R9C10[0][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/cats_r_21_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path23
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/q0_2_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R4C8[2][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/q0_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R4C8[2][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/q0_2_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/q0_2_s0 | |||
0.666 | 0.018 | tHld | 1 | R4C8[2][B] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/q0_2_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path24
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_6_s1 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R17C10[0][B] | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R17C10[0][B] | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_6_s1/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_6_s1 | |||
0.666 | 0.018 | tHld | 1 | R17C10[0][B] | u_psram_top/u_psram_top/u_psram_init/timer_cnt1_6_s1 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Path25
Path Summary:
Slack | 3.934 |
Data Arrival Time | 4.605 |
Data Required Time | 0.671 |
From | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
To | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_15_s0 |
Launch Clk | clk.default_clk:[R] |
Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk.default_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR9[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 55 | IOR9[A] | clk_ibuf/O |
1.032 | 0.222 | tNET | RR | 1 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/CLK |
1.432 | 0.400 | tC2Q | RF | 3 | R4C2[0][A] | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0/Q |
1.722 | 0.290 | tNET | FF | 1 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/I1 |
2.389 | 0.667 | tINS | FR | 497 | R5C2[0][B] | u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1/F |
4.605 | 2.216 | tNET | RR | 1 | R5C8[1][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | ||||
0.396 | 0.396 | tCL | RR | 1919 | LEFTSIDE[0] | u_psram_top/u_psram_top/clkdiv/CLKOUT |
0.618 | 0.222 | tNET | RR | 1 | R5C8[1][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_15_s0/CLK |
0.648 | 0.030 | tUnc | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_15_s0 | |||
0.666 | 0.018 | tHld | 1 | R5C8[1][A] | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_en_delay_all_15_s0 |
Path Statistics:
Clock Skew | -0.414 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 78.539%; route: 0.222, 21.461% |
Arrival Data Path Delay | cell: 0.667, 18.674%; route: 2.506, 70.131%; tC2Q: 0.400, 11.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.222, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0/CLK |
MPW2
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK |
MPW3
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK |
MPW4
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
MPW5
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_la0_top/data_register_136_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_la0_top/data_register_136_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_la0_top/data_register_136_s0/CLK |
MPW6
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_la0_top/data_register_104_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_la0_top/data_register_104_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_la0_top/data_register_104_s0/CLK |
MPW7
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_la0_top/data_register_88_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_la0_top/data_register_88_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_la0_top/data_register_88_s0/CLK |
MPW8
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_la0_top/data_register_80_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_la0_top/data_register_80_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_la0_top/data_register_80_s0/CLK |
MPW9
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_la0_top/data_register_76_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_la0_top/data_register_76_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_la0_top/data_register_76_s0/CLK |
MPW10
MPW Summary:
Slack: | 2.588 |
Actual Width: | 4.088 |
Required Width: | 1.500 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | gw_gao_inst_0/u_la0_top/data_register_74_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK | ||
5.000 | 0.000 | tCL | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
5.000 | 0.000 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
7.071 | 2.071 | tNET | FF | gw_gao_inst_0/u_la0_top/data_register_74_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK | ||
10.000 | 0.000 | tCL | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
10.000 | 0.000 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
11.159 | 1.159 | tNET | RR | gw_gao_inst_0/u_la0_top/data_register_74_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1919 | clk_ao | -7.569 | 0.315 |
642 | gao_jtag_tck | -9.208 | 2.071 |
515 | uart_counter[6] | -4.139 | 6.216 |
497 | ddr_rst | -7.459 | 4.736 |
260 | uart_counter[5] | -3.569 | 6.264 |
190 | n20_3 | -0.543 | 3.754 |
170 | data_out_shift_reg_167_7 | -7.903 | 4.335 |
169 | n1536_5 | -7.903 | 3.752 |
167 | init_calib | -7.569 | 8.389 |
133 | uart_counter[4] | -3.656 | 7.672 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R9C31 | 88.89% |
R9C32 | 87.50% |
R21C18 | 79.17% |
R16C18 | 77.78% |
R20C19 | 73.61% |
R16C19 | 73.61% |
R7C6 | 70.83% |
R15C18 | 70.83% |
R21C20 | 66.67% |
R17C18 | 66.67% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|