Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\gowin_rpll\gowin_rpll.v E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\key_debounce.v E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psram_memory_interface\psram_memory_interface.v E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psram_test.v E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psramwork.v E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\uart_sendout.v D:\programmer\gowin\Gowin_V1.9.6.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\programmer\gowin\Gowin_V1.9.6.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\programmer\gowin\Gowin_V1.9.6.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\programmer\gowin\Gowin_V1.9.6.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\programmer\gowin\Gowin_V1.9.6.02Beta\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\programmer\gowin\Gowin_V1.9.6.02Beta\IDE\data\ipcores\gw_jtag.v E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Verision | GowinSynthesis V1.9.6.02Beta |
Created Time | Thu Oct 01 20:52:12 2020 |
Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved. |
Design Settings
Top Level Module: | psramwork |
Part Number: | GW1NR-LV9LQ144PC5/I4 |
Resource
Resource Usage Summary
I/OPORT Usage: | 8 |
Emedded PORT Usage: | 26 |
I/OBUF Usage: | 33 |
    IBUF | 6 |
    OBUF | 8 |
    IOBUF | 18 |
    ELVDS_OBUF | 1 |
REG Usage: | 2458 |
    DFF | 159 |
    DFFE | 1025 |
    DFFS | 1 |
    DFFSE | 1 |
    DFFR | 44 |
    DFFRE | 15 |
    DFFP | 3 |
    DFFPE | 41 |
    DFFC | 354 |
    DFFCE | 801 |
    DFFNP | 2 |
    DFFNC | 4 |
    DL | 8 |
LUT Usage: | 2240 |
    LUT2 | 337 |
    LUT3 | 1061 |
    LUT4 | 842 |
MUX Usage: | 1 |
    MUX16 | 1 |
ALU Usage: | 85 |
    ALU | 85 |
SSRAM Usage: | 18 |
    RAM16SDP4 | 18 |
INV Usage: | 11 |
    INV | 11 |
IOLOGIC Usage: | 58 |
    IDES4 | 16 |
    OSER4 | 23 |
    IODELAY | 19 |
BSRAM Usage: | 9 |
    SDPX9B | 9 |
CLOCK Usage: | 2 |
    CLKDIV | 1 |
    rPLL | 1 |
Resource Utilization Summary
Target Device: GW1NR-9-LQFP144PCFU Logics | 2452(2259 LUTs, 85 ALUs, 18 SSRAMs) / 8640 | 28% |
Registers | 2458 / 6921 | 36% |
BSRAMs | 9 / 26 | 35% |
DSP Macros | 0 / (5*2) | 0% |
Timing
Clock Summary:
Clock | Type | Frequency | Period | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk.default_clk | Base | 50.0 MHz | 20.000 | 0.000 | 10.000 | clk_ibuf/I | ||
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 160.0 MHz | 6.250 | 0.000 | 3.125 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUT |
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 160.0 MHz | 6.250 | 0.000 | 3.125 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUTP |
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 80.0 MHz | 12.500 | 0.000 | 6.250 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUTD |
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 53.3 MHz | 18.750 | 0.000 | 9.375 | clk_ibuf/I | clk.default_clk | Gowin_rPLL_inst/rpll_inst/CLKOUTD3 |
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 80.0 MHz | 12.500 | 0.000 | 6.250 | Gowin_rPLL_inst/rpll_inst/CLKOUT | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk | u_psram_top/u_psram_top/clkdiv/CLKOUT |
Timing Report:
Top View: | psramwork |
Requested Frequency: | 50.0 MHz |
Paths Requested: | 5 |
Constraint File(ignored): |
Performance Summary:
Worst Slack in Design: 9.217Start Clock | Slack | Requested Frequency | Estimated Frequency | Requested Period | Estimated Period | Clock Type |
---|---|---|---|---|---|---|
clk.default_clk | 9.217 | 50.0 MHz | 92.7 MHz | 20.000 | 10.783 | Base |
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | -0.271 | 80.0 MHz | 78.3 MHz | 12.500 | 12.771 | Generated |
Detail Timing Paths Information
Path information for path number 1 : Clock Skew: | 0.078 |
Setup Relationship: | 0.625 |
Slack(critical): | -2.407 |
Data Arrival Time: | 4.399 |
Data Required Time: | 1.992 |
Number of Logic Level: | 2 |
Starting Point: | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
Ending Point: | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 |
The Start Point Is Clocked By: | clk.default_clk[falling] |
The End Point Is Clocked By: | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[rising] |
Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
---|---|---|---|---|---|---|
clk_ibuf | IBUF | I | In | - | 0.000 | - |
clk_ibuf | IBUF | O | Out | 0.943 | 0.943 | - |
clk_d | Net | - | - | 0.436 | - | 55 |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | CLK | In | - | 1.378 | - |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | Q | Out | 0.550 | 1.928 | - |
dll_rst | Net | - | - | 0.576 | - | 3 |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | I1 | In | - | 2.504 | - |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | F | Out | 1.319 | 3.823 | - |
ddr_rst | Net | - | - | 0.576 | - | 497 |
\u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[2].dq_oser4 | OSER4 | RESET | In | - | 4.399 | - |
Total Path Delay: 4.399
Logic Delay: 2.811(63.9%)
Route Delay: 1.588(36.1%)
Path information for path number 2 : 
Clock Skew: | 0.156 |
Setup Relationship: | 0.625 |
Slack(non-critical): | -2.407 |
Data Arrival Time: | 4.399 |
Data Required Time: | 1.992 |
Number of Logic Level: | 2 |
Starting Point: | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
Ending Point: | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4 |
The Start Point Is Clocked By: | clk.default_clk[falling] |
The End Point Is Clocked By: | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[rising] |
Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
---|---|---|---|---|---|---|
clk_ibuf | IBUF | I | In | - | 0.000 | - |
clk_ibuf | IBUF | O | Out | 0.943 | 0.943 | - |
clk_d | Net | - | - | 0.436 | - | 55 |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | CLK | In | - | 1.378 | - |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | Q | Out | 0.550 | 1.928 | - |
dll_rst | Net | - | - | 0.576 | - | 3 |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | I1 | In | - | 2.504 | - |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | F | Out | 1.319 | 3.823 | - |
ddr_rst | Net | - | - | 0.576 | - | 497 |
\u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[1].dq_oser4 | OSER4 | RESET | In | - | 4.399 | - |
Total Path Delay: 4.399
Logic Delay: 2.811(63.9%)
Route Delay: 1.588(36.1%)
Path information for path number 3 : 
Clock Skew: | 0.234 |
Setup Relationship: | 0.625 |
Slack(non-critical): | -2.407 |
Data Arrival Time: | 4.399 |
Data Required Time: | 1.992 |
Number of Logic Level: | 2 |
Starting Point: | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
Ending Point: | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4 |
The Start Point Is Clocked By: | clk.default_clk[falling] |
The End Point Is Clocked By: | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[rising] |
Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
---|---|---|---|---|---|---|
clk_ibuf | IBUF | I | In | - | 0.000 | - |
clk_ibuf | IBUF | O | Out | 0.943 | 0.943 | - |
clk_d | Net | - | - | 0.436 | - | 55 |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | CLK | In | - | 1.378 | - |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | Q | Out | 0.550 | 1.928 | - |
dll_rst | Net | - | - | 0.576 | - | 3 |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | I1 | In | - | 2.504 | - |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | F | Out | 1.319 | 3.823 | - |
ddr_rst | Net | - | - | 0.576 | - | 497 |
\u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[0].dq_oser4 | OSER4 | RESET | In | - | 4.399 | - |
Total Path Delay: 4.399
Logic Delay: 2.811(63.9%)
Route Delay: 1.588(36.1%)
Path information for path number 4 : 
Clock Skew: | 0.313 |
Setup Relationship: | 0.625 |
Slack(non-critical): | -2.407 |
Data Arrival Time: | 4.399 |
Data Required Time: | 1.992 |
Number of Logic Level: | 2 |
Starting Point: | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
Ending Point: | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4 |
The Start Point Is Clocked By: | clk.default_clk[falling] |
The End Point Is Clocked By: | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[rising] |
Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
---|---|---|---|---|---|---|
clk_ibuf | IBUF | I | In | - | 0.000 | - |
clk_ibuf | IBUF | O | Out | 0.943 | 0.943 | - |
clk_d | Net | - | - | 0.436 | - | 55 |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | CLK | In | - | 1.378 | - |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | Q | Out | 0.550 | 1.928 | - |
dll_rst | Net | - | - | 0.576 | - | 3 |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | I1 | In | - | 2.504 | - |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | F | Out | 1.319 | 3.823 | - |
ddr_rst | Net | - | - | 0.576 | - | 497 |
\u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cs_oser4 | OSER4 | RESET | In | - | 4.399 | - |
Total Path Delay: 4.399
Logic Delay: 2.811(63.9%)
Route Delay: 1.588(36.1%)
Path information for path number 5 : 
Clock Skew: | 0.391 |
Setup Relationship: | 0.625 |
Slack(non-critical): | -2.407 |
Data Arrival Time: | 4.399 |
Data Required Time: | 1.992 |
Number of Logic Level: | 2 |
Starting Point: | u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 |
Ending Point: | u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4 |
The Start Point Is Clocked By: | clk.default_clk[falling] |
The End Point Is Clocked By: | Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[rising] |
Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
---|---|---|---|---|---|---|
clk_ibuf | IBUF | I | In | - | 0.000 | - |
clk_ibuf | IBUF | O | Out | 0.943 | 0.943 | - |
clk_d | Net | - | - | 0.436 | - | 55 |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | CLK | In | - | 1.378 | - |
\u_psram_top/u_psram_top/u_psram_sync/dll_rst_s0 | DFFP | Q | Out | 0.550 | 1.928 | - |
dll_rst | Net | - | - | 0.576 | - | 3 |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | I1 | In | - | 2.504 | - |
\u_psram_top/u_psram_top/u_psram_sync/ddr_rst_s1 | LUT2 | F | Out | 1.319 | 3.823 | - |
ddr_rst | Net | - | - | 0.576 | - | 497 |
\u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4 | OSER4 | RESET | In | - | 4.399 | - |
Total Path Delay: 4.399
Logic Delay: 2.811(63.9%)
Route Delay: 1.588(36.1%)
Summary
Total Warnings: | 17 |
Total Informations: | 67 |
Synthesis completed successfully!
Process took 0h:0m:8s realtime, 0h:0m:7s cputime
Memory peak: 199.5MB