Power Messages

Report Title Gowin Power Analysis Report
Design File E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\impl\gwsynthesis\psramwork.vg
Physical Constraints File E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psramwork.cst
Timing Constraints File E:\design\gowin_develop\gowin_144develop\codeproject\psramwork\project\psramwork\src\psramwork.sdc
GOWIN Version V1.9.6.02Beta
Part Number GW1NR-LV9LQ144PC5/I4
Created Time Thu Oct 01 20:52:29 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 127.994
Quiescent Power (mW) 3.943
Dynamic Power (mW) 124.051
Psram Power (mW) 86.000

Thermal Information:

Junction Temperature 26.341
Theta JA 10.500
Max Allowed Ambient Temperature 83.656

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.200 101.163 2.436 124.319
VCCX 2.500 0.600 0.234 2.084
VCCO18 1.800 0.543 0.217 1.369
VCCO33 3.300 0.054 0.013 0.222

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 9.095 NA 10.357
IO 4.735 1.300 20.343
BSRAM 32.854 NA NA
PLL 4.463 NA NA
DLL 9.830 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW) Routing Dynamic Power(mW)
psramwork 91.442 27.038(27.038) 64.404(64.310)
psramwork/Gowin_rPLL_inst/ 4.667 4.463(0.000) 0.204(0.000)
psramwork/gw_gao_inst_0/ 28.170 6.100(6.100) 22.070(21.676)
psramwork/gw_gao_inst_0/u_icon_top/ 0.317 0.028(0.000) 0.289(0.000)
psramwork/gw_gao_inst_0/u_la0_top/ 27.460 6.073(4.143) 21.387(6.890)
psramwork/gw_gao_inst_0/u_la0_top/u_ao_crc32/ 0.568 0.137(0.000) 0.431(0.000)
psramwork/gw_gao_inst_0/u_la0_top/u_ao_match_0/ 0.124 0.020(0.000) 0.104(0.000)
psramwork/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ 10.342 3.986(0.000) 6.355(0.000)
psramwork/u5/ 0.404 0.222(0.000) 0.182(0.000)
psramwork/u_psram_top/ 35.692 13.269(13.132) 22.423(18.078)
psramwork/u_psram_top/u_psram_top/ 31.209 13.132(2.890) 18.078(15.664)
psramwork/u_psram_top/u_psram_top/u_psram_init/ 8.297 1.627(0.000) 6.670(0.000)
psramwork/u_psram_top/u_psram_top/u_psram_sync/ 0.888 0.120(0.000) 0.768(0.000)
psramwork/u_psram_top/u_psram_top/u_psram_wd/ 9.369 1.143(0.922) 8.226(8.006)
psramwork/u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ 5.545 0.542(0.000) 5.003(0.000)
psramwork/u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/ 3.383 0.381(0.000) 3.002(0.000)
psramwork/u_test/ 21.416 2.690(0.000) 18.726(0.000)
psramwork/u_uart_sendout/ 0.998 0.294(0.000) 0.705(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
DEFAULT_CLK 100.000 20.256
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk 80.000 55.041
clk.default_clk 50.000 5.865
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk 160.000 10.252