Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\program\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v
D:\program\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\PSRAM\data\psram_code_9k.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.6.02Beta
Created Time Mon Aug 31 15:12:57 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: PSRAM_Memory_Interface_Top
Part Number: GW1NR-LV9LQ144PC5/I4

Resource

Resource Usage Summary

I/OPORT Usage: 166
Emedded PORT Usage: 26
I/OBUF Usage: 191
    IBUF 99
    OBUF 73
    IOBUF 18
    ELVDS_OBUF 1
REG Usage: 562
    DFFP 2
    DFFPE 8
    DFFC 323
    DFFCE 221
    DL 8
LUT Usage: 978
    LUT2 248
    LUT3 347
    LUT4 383
ALU Usage: 46
    ALU 46
SSRAM Usage: 18
    RAM16SDP4 18
INV Usage: 5
    INV 5
IOLOGIC Usage: 58
    IDES4 16
    OSER4 23
    IODELAY 19
CLOCK Usage: 1
    CLKDIV 1

Resource Utilization Summary

Target Device: GW1NR-9-LQFP144P
CFU Logics 1137(983 LUTs, 46 ALUs, 18 SSRAMs) / 8640 13%
Registers 562 / 6921 8%
BSRAMs 0 / 26 0%
DSP Macros 0 / (5*2) 0%


Timing

Clock Summary:

Clock Type Frequency Period Rise Fall Source Master Object
u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 50.0 MHz 20.000 0.000 10.000 memory_clk_ibuf/I DEFAULT_CLK u_psram_top/clkdiv/CLKOUT
DEFAULT_CLK Base 100.0 MHz 10.000 0.000 5.000 memory_clk_ibuf/I clk_ibuf/I

Timing Report:

Top View: PSRAM_Memory_Interface_Top
Requested Frequency: 50.0 MHz
Paths Requested: 5
Constraint File(ignored):
All time values displayed in nanoseconds(ns).

Performance Summary:

Worst Slack in Design: 9.873
Start Clock Slack Requested Frequency Estimated Frequency Requested Period Estimated Period Clock Type
u_psram_top/clkdiv/CLKOUT.default_gen_clk 9.873 50.0 MHz 98.7 MHz 20.000 10.127 Generated

Detail Timing Paths Information

Path information for path number 1 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(critical): -0.783
Data Arrival Time: 11.646
Data Required Time: 10.863
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_s3
Ending Point: u_psram_top/u_psram_sync/lock_cnt_12_s3
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf IBUF I In - 0.000 -
clk_ibuf IBUF O Out 0.943 0.943 -
clk_d Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC Q Out 0.550 1.928 -
lock_cnt[1] Net - - 0.576 - 5
\u_psram_top/u_psram_sync/n47_s2 LUT4 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n47_s2 LUT4 F Out 1.319 3.823 -
n47_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n44_s3 LUT4 I1 In - 4.399 -
\u_psram_top/u_psram_sync/n44_s3 LUT4 F Out 1.319 5.718 -
n44_8 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_s2 LUT2 I1 In - 6.294 -
\u_psram_top/u_psram_sync/n43_s2 LUT2 F Out 1.319 7.613 -
n43_6 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n39_s2 LUT4 I2 In - 8.189 -
\u_psram_top/u_psram_sync/n39_s2 LUT4 F Out 0.986 9.175 -
n39_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n39_s5 LUT4 I1 In - 9.751 -
\u_psram_top/u_psram_sync/n39_s5 LUT4 F Out 1.319 11.070 -
n39_11 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_12_s3 DFFC D In - 11.646 -

Total Path Delay: 11.646
Logic Delay: 7.754(66.6%)
Route Delay: 3.892(33.4%)


Path information for path number 2 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): -0.783
Data Arrival Time: 11.646
Data Required Time: 10.863
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_s3
Ending Point: u_psram_top/u_psram_sync/lock_cnt_13_s1
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf IBUF I In - 0.000 -
clk_ibuf IBUF O Out 0.943 0.943 -
clk_d Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC Q Out 0.550 1.928 -
lock_cnt[1] Net - - 0.576 - 5
\u_psram_top/u_psram_sync/n47_s2 LUT4 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n47_s2 LUT4 F Out 1.319 3.823 -
n47_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n44_s3 LUT4 I1 In - 4.399 -
\u_psram_top/u_psram_sync/n44_s3 LUT4 F Out 1.319 5.718 -
n44_8 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_s2 LUT2 I1 In - 6.294 -
\u_psram_top/u_psram_sync/n43_s2 LUT2 F Out 1.319 7.613 -
n43_6 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n39_s2 LUT4 I2 In - 8.189 -
\u_psram_top/u_psram_sync/n39_s2 LUT4 F Out 0.986 9.175 -
n39_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n38_s1 LUT4 I1 In - 9.751 -
\u_psram_top/u_psram_sync/n38_s1 LUT4 F Out 1.319 11.070 -
n38_5 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_13_s1 DFFCE D In - 11.646 -

Total Path Delay: 11.646
Logic Delay: 7.754(66.6%)
Route Delay: 3.892(33.4%)


Path information for path number 3 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): -0.702
Data Arrival Time: 11.565
Data Required Time: 10.863
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_s3
Ending Point: u_psram_top/u_psram_sync/lock_cnt_14_s1
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf IBUF I In - 0.000 -
clk_ibuf IBUF O Out 0.943 0.943 -
clk_d Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC Q Out 0.550 1.928 -
lock_cnt[1] Net - - 0.576 - 5
\u_psram_top/u_psram_sync/n47_s2 LUT4 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n47_s2 LUT4 F Out 1.319 3.823 -
n47_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n44_s3 LUT4 I1 In - 4.399 -
\u_psram_top/u_psram_sync/n44_s3 LUT4 F Out 1.319 5.718 -
n44_8 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_s2 LUT2 I1 In - 6.294 -
\u_psram_top/u_psram_sync/n43_s2 LUT2 F Out 1.319 7.613 -
n43_6 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n39_s2 LUT4 I2 In - 8.189 -
\u_psram_top/u_psram_sync/n39_s2 LUT4 F Out 0.986 9.175 -
n39_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n37_s1 LUT4 I0 In - 9.751 -
\u_psram_top/u_psram_sync/n37_s1 LUT4 F Out 1.238 10.989 -
n37_5 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_14_s1 DFFCE D In - 11.565 -

Total Path Delay: 11.565
Logic Delay: 7.674(66.4%)
Route Delay: 3.892(33.6%)


Path information for path number 4 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): -0.450
Data Arrival Time: 11.313
Data Required Time: 10.863
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_s3
Ending Point: u_psram_top/u_psram_sync/lock_cnt_15_s1
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf IBUF I In - 0.000 -
clk_ibuf IBUF O Out 0.943 0.943 -
clk_d Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_s3 DFFC Q Out 0.550 1.928 -
lock_cnt[1] Net - - 0.576 - 5
\u_psram_top/u_psram_sync/n47_s2 LUT4 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n47_s2 LUT4 F Out 1.319 3.823 -
n47_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n44_s3 LUT4 I1 In - 4.399 -
\u_psram_top/u_psram_sync/n44_s3 LUT4 F Out 1.319 5.718 -
n44_8 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_s2 LUT2 I1 In - 6.294 -
\u_psram_top/u_psram_sync/n43_s2 LUT2 F Out 1.319 7.613 -
n43_6 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n39_s2 LUT4 I2 In - 8.189 -
\u_psram_top/u_psram_sync/n39_s2 LUT4 F Out 0.986 9.175 -
n39_6 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n36_s1 LUT4 I2 In - 9.751 -
\u_psram_top/u_psram_sync/n36_s1 LUT4 F Out 0.986 10.737 -
n36_5 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_15_s1 DFFCE D In - 11.313 -

Total Path Delay: 11.313
Logic Delay: 7.422(65.6%)
Route Delay: 3.892(34.4%)


Path information for path number 5 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 0.588
Data Arrival Time: 10.275
Data Required Time: 10.863
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/count_2_s0
Ending Point: u_psram_top/u_psram_sync/count_0_s0
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf IBUF I In - 0.000 -
clk_ibuf IBUF O Out 0.943 0.943 -
clk_d Net - - 0.436 - 31
\u_psram_top/u_psram_sync/count_2_s0 DFFC CLK In - 1.378 -
\u_psram_top/u_psram_sync/count_2_s0 DFFC Q Out 0.550 1.928 -
count[2] Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n285_s16 LUT2 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n285_s16 LUT2 F Out 1.319 3.823 -
n285_20 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n327_s13 LUT4 I3 In - 4.399 -
\u_psram_top/u_psram_sync/n327_s13 LUT4 F Out 0.751 5.150 -
n327_17 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n414_s3 LUT4 I3 In - 5.726 -
\u_psram_top/u_psram_sync/n414_s3 LUT4 F Out 0.751 6.477 -
n414_7 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/n414_s2 LUT4 I3 In - 7.053 -
\u_psram_top/u_psram_sync/n414_s2 LUT4 F Out 0.751 7.805 -
n414_6 Net - - 0.576 - 3
\u_psram_top/u_psram_sync/n414_s1 LUT2 I1 In - 8.381 -
\u_psram_top/u_psram_sync/n414_s1 LUT2 F Out 1.319 9.699 -
n414_5 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/count_0_s0 DFFC D In - 10.275 -

Total Path Delay: 10.275
Logic Delay: 6.384(62.1%)
Route Delay: 3.892(37.9%)


Summary

Total Warnings: 13
Total Informations: 71

Synthesis completed successfully!
Process took 0h:0m:5s realtime, 0h:0m:4s cputime
Memory peak: 49.6MB