counter Project Status
Project File: counter.xise Parser Errors: No Errors
Module Name: counter Implementation State: Synthesized
Target Device: xc5vlx330-2ff1760
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 2 207360 0%
Number of Slice LUTs 3 207360 0%
Number of fully used LUT-FF pairs 0 5 0%
Number of bonded IOBs 0 1200 0%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期日 二月 13 00:11:08 2011001 Info (1 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 02/13/2011 - 00:12:55
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