System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 < data not available > < data not available > < data not available >
Path C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.3\ISE_DS\common\bin\nt;
C:\Xilinx\12.3\ISE_DS\common\lib\nt;
C:\WINDOWS;
C:\WINDOWS\system32;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Cadence Design Systems\IUS\tools\bin;
C:\Program Files\Cadence Design Systems\IUS\tools\lib;
C:\Novas\Debussy\bin;
c:\altera\10.1\quartus\bin;
C:\Program Files\Borland\CBuilder6\Bin;
C:\Program Files\Borland\CBuilder6\Projects\Bpl;
C:\Program Files\Intel\Wireless\Bin\;
C:\Program Files\ThinkPad\ConnectUtilities;
C:\Program Files\QuickTime\QTSystem\;
C:\Program Files\Microsoft Visual Studio\Common\Tools\WinNT;
C:\Program Files\Microsoft Visual Studio\Common\MSDev98\Bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools;
C:\Program Files\Microsoft Visual Studio\VC98\bin;
C:\Program Files\Modeltech_6.1f\win32;
C:\Program Files\Synplicity\fpga_962\bin\;
C:\Modeltech_6.3e\win32		 < data not available > < data not available > < data not available >
XILINX C:\Xilinx\12.3\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINXD_LICENSE_FILE C:\Xilinx\12.3\Xilinx.lic < data not available > < data not available > < data not available >
XILINX_DSP C:\Xilinx\12.3\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_EDK C:\Xilinx\12.3\ISE_DS\EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD C:\Xilinx\12.3\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   counter.prj  
-ifmt   mixed MIXED
-ofn   counter  
-ofmt   NGC NGC
-p   xc5vlx330-2-ff1760  
-top   counter  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO NO
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-dsp_utilization_ratio DSP Utilization Ratio 100 100%
-reduce_control_sets   Off OFF
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-use_dsp48   Auto AUTO
-iobuf   NO YES
-max_fanout   100000 100000
-bufg   0 32
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Auto AUTO
-use_sync_set   Auto AUTO
-use_sync_reset   Auto AUTO
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz/2194 MHz <  data not available  > <  data not available  > <  data not available  >
Host oomusoux61 <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft Windows XP Professional <  data not available  > <  data not available  > <  data not available  >
OS Release Service Pack 3 (build 2600) <  data not available  > <  data not available  > <  data not available  >