counter Project Status | |||
Project File: | counter.xise | Parser Errors: | No Errors |
Module Name: | counter | Implementation State: | Synthesized |
Target Device: | xc5vlx330-2ff1760 |
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No Errors |
Product Version: | ISE 12.3 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 2 | 207360 | 0% | |
Number of Slice LUTs | 3 | 207360 | 0% | |
Number of fully used LUT-FF pairs | 0 | 5 | 0% | |
Number of bonded IOBs | 0 | 1200 | 0% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 星期日 二月 13 00:11:08 2011 | 0 | 0 | 1 Info (1 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |